TMSC unveils 40nm 'half-node' step to 32nm

The semiconductor industry's first 40nm foundry process has been unveiled by Taiwan Semiconductor Manufacturing Co. Ltd. The process is an interim, "half-node" step toward the 32nm process node, which TSMC expects to ramp starting late next year.
Even as the world's largest silicon foundry pushes the envelope, it is quietly changing its leading-edge process strategy, as its customers—squeezed by soaring IC design and manufacturing costs—slow their migration to next-generation foundry processes.

The trend has been seen across the industry, with negative implications for foundry margins and growth.

Traditionally, TSMC would install and ramp significant capacity for each successive process node. But last year, during the shift to 45nm, TSMC discovered that the anticipated "demand for leading-edge capacity was not there," said Jim Hines, an analyst with Gartner Inc. Foundry customers are "not migrating to the advanced nodes as fast as before."

Playing safe
To lessen its risk, TSMC now ramps a "minimum" amount of leading-edge capacity, sizing up demand for a given process node before jumping in with both feet, Hines said.

That prudent strategy helps TSMC sustain its envious margins, but it also gives the appearance that foundries are reluctant to invest in leading-edge capacity. Indeed, at a recent event, G. Dan Hutcheson, CEO of VLSI Research Inc. observed that foundry providers "have fallen off Moore's Law"; they are "backing away from aggressive scaling."

The foundry model is far from broken, but the business is rapidly changing. During the fabless boom of the 1990s, foundry providers emerged and grew at an astonishing rate. At the time, the foundries were at least two to three technology nodes behind the leading IDMs. But the outsourcing specialists were also able to obtain capital at competitive rates.

Until recently, the leading-edge foundries—Chartered Semiconductor Manufacturing, TSMC, United Microelectronics Corp. and, to a degree, IBM—built fab capacity at brisk rates during both upturns and downturns. That strategy, not surprisingly, resulted in extreme oversupply/undersupply cycles within the sector.

Today, most foundries push their processes to the leading edge but adhere to a more-conservative ramp schedule that builds out capacity in line with tangible demand. The exception to the rule appears to be China's Semiconductor Manufacturing International Corp., which continues to expand capacity despite the dip in the market.

"I think the foundry guys have the right strategy. They are saying: 'Look, it's not all about growth; it's about profitability.' So they are going to build more to demand than forecast," said Tom Caulfield, executive VP for sales, marketing and customer service at chip-equipment supplier Novellus Systems Inc.

Runaway costs
Foundries and IDMs are also seeing another ominous trend: IC design, photomask and process costs continue to soar with each successive technology node. But foundries must continue to funnel R&D dollars into such emerging technologies as high-k dielectrics and metal gates.

On the bright side, even as leading-edge customers prove slower on the uptake for next-node processes, foundry providers continue to see surprisingly high demand for older, lower-cost process technologies at their 200mm fabs.

TSMC and its competitors have recognized the bifurcation of the customer base and have acted accordingly. Some observers nonetheless wonder whether the foundries will prove nimble enough to hit the market with the right processes when the next upswing inevitably occurs.

TSMC, for its part, recently split its operations into two groups, respectively supporting its leading- and trailing-edge technology efforts: the Advanced Technology Business Organization and the Mainstream Technology Business Organization.

For its advanced-technology customers, TSMC will continue to push the process envelope. The company unveiled its 45nm process in 2007 and has recently tipped details about its 32nm technology. But the latter process is not slated to roll until the latter part of 2009. Hence the new 40nm process, which will serve leading-edge requirements in the interim.

Advanced offerings
The offering is in fact two processes: 40G, a general-purpose process, and 40LP, for low-power requirements. The SRAM cell size for the technology is said to be the smallest in the industry, at 0.242µm². The 40nm technology is said to offer 2.35 times the gate density of TSMC's 65nm process. The transition from 45nm to 40nm low-power technology reduces power scaling by up to 15 percent, TSMC said.

The foundry developed 40LP for leakage-sensitive applications such as wireless and portable devices. Its 40G variant targets performance applications such as processors, graphic processing units, game console ICs, networking and FPGA designs.

"Our design flow can take a design started at 45nm and target it toward the advantages of 40nm," said John Wei, senior director of advanced technology marketing at TSMC. "A lot of TSMC development work has gone into ensuring that this transition is transparent."

The 40nm process employs 193nm immersion lithography and ultralow-k material. The logic family includes a low-power, triple-gate oxide (LPG) option to support high-performance wireless and portable applications. Both the G and the LP processes offer multiple-Vt core devices and 1.8V/2.5V I/O options to meet different product requirements.

TSMC will offer a multiproject wafer program at the 40nm half-node to reduce costs. The processes support a range of third-party intellectual property and EDA tools as well as TSMC's own IP. First wafers are expected in Q2 08.

This is not the foundry's first half-node process step. It released its 65nm process in 2006 and followed up with a 55nm half-node entry before rolling its 45nm technology last year.

- Mark LaPedus
EE Times