Coming soon: Intel's six-core chips‏

Pat Gelsinger, Intel Corp.'s digital enterprise group general manager, tipped the press last week about a host of upcoming processors, including Tukwila, Dunnington and Nehalem.
With the set slides available on the Intel Website, Gelsinger discussed servers based on Intel's six-core Dunnington processor and Tukwila processor.

It is not clear from Gelsinger's slides what processor core Tukwila is based on, but the slide states that it is a quad-core device with a 30Mbyte cache and two billion transistors. It will also include a QuickPath interconnect (QPI), Intel's replacement for the front-side bus. The Tukwila is expected to provide more than twice the performance of a dual-core Itanium processor with the number 9100. However, Gelsinger's presentation did not show the process technology node or the clock frequency of either for comparison.

Gelsinger provided more information about Dunnington but did not disclose the maximum clock frequency. The six-core Dunnington is being implemented using 1.9 billion transistors in 45nm CMOS process technology, has a 16Mbyte level-three cache memory and is due to become available in the 2H 08, he said.

Nehalem is a micro-architecture which is intended to support the design of processors on 45nm process technology and below, according to the presentation but was not made clear whether Nehalem is the name of the core processor or the architecture, or both. Again in the presentation Gelsinger said nothing about clock frequency, which is fundamental to judging performance.

Nehalem-style processors will be scalable from two to eight cores, Gelsinger said in his presentation. It will support multithreading, resulting in 4 to 16 thread capability. Nehalem will deliver four times the memory bandwidth compared to the Intel Xeon processor-based systems. With up to 8Mbytes of level-3 cache, QPI capable of transmitting data at up to 25.6GBps, the Nehalem chips will eventually scale from notebooks to high-performance servers.

Visual computing
Gelsinger also put up slides about visual computing arguing that realistic graphics and high-definition video are a good use of multiprocessor architectures and will do well when accompanied by developer tools. He then introduced the Larrabee architecture for visual computing.

Gelsinger further discussed Intel's advanced vector extensions, which are expected to increase performance in floating point, media, and processor intensive software. He said the company would make the detailed specification public in April at the Intel Developer Forum in Shanghai and that the instructions will be implemented in the microarchitecture codenamed "Sandy Bridge" in the 2010 timeframe.

- Peter Clarke
EE Times Europe