IBM splashes water on hot 3D chips

IBM's Zurich Research Laboratory recently demonstrated 3D chip stacks that are cooled with water. The company expects to commercialize such stacks for its multicore servers as early as 2013.

IBM plans to stack memory chips between processor cores to multiply interconnections by 100 times while reducing their feature size tenfold. To cool the stack at a rate of 180W per layer, water flows down 50µ channels between the stacked chips.

"Electrical interconnects are in a wiring crisis. The wiring does not scale the way transistors do it because the wire width is shrinking while their length is not," said Thomas Brunschwiler, researcher, IBM Zurich. "Our solution is to go to 3D to stack multicore dice and have the interconnections go in between them vertically, which can decrease their length by up to 1,000 times," he added.

IBM's paper on the approach, "Forced convective interlayer cooling in vertically integrated packages," received a Best Paper award at the IEEE ITherm conference, held recently in Florida. This marked the third consecutive year that the IBM's Advanced Thermal Packaging team has won the awards. The Zurich group claimed to be fixated on water cooling because it is up to 4,000 times more effective than air in removing heat from electronics.

Early this year, the same group described the water cooling method for IBM's Hydro-Cluster supercomputer. For the Hydro-Cluster Power 575, the group replaced heat sinks with water-filled copper plates above each core. The team predicted high-end IBM multicore computers would migrate from the copper-plate water-cooling method to the 3D chip-stack in five to 10 years.

The 3D water-cooled chip stacks will interleave processor cores and memory chips so that interconnects run vertically chip-to-chip through copper vias that are surrounded by silicon oxide. Thin-film soldering (using electroplating) enables the separate dice to be electrically bonded to the layers above and below them, with the insulating layers of silicon oxide separating the flowing water from the copper vias.

The power density dramatically increases for such 3D chip stacks, since enough heat gets trapped between layers to melt the cores. To solve the problem, IBM etched a liquid aqueduct into the silicon oxide on the back each die. This creates a water-filled separating cavity with 10,000 pillars, each housing a copper via surrounded by silicon oxide. The cooling technique runs water through the aqueduct between each layer in the chip stack, enabling IBM to channel heat away from 3D multichip stacks of nearly any scale.

"The technology forces water between the layers in the chip stack, picking up the heat right at its source," said Brunschwiler. "We found that to create an efficient heat remover, we had to use a structure with very little resistance to the fluid flow. We found that round pillars aligned in the flow direction and put under pressure gave the best convective heat transfer," he added.

IBM packages the chip stacks in sealed pressurized silicon housing with an inlet reservoir on one side and an outlet reservoir on the other. The only way water can get from the inlet side of the silicon box to its outlet side is by going through the silicon oxide layers separating the layers of the 3D stack. Cool water enters a 3D chip stack and exits heated. The protected copper vias connect the chips vertically. After being forced through the layers between the chips in a stack, the heated water could be fed to the hot tap of the customer's plumbing, turning a data center's wasted heat into a means for reducing the data center's carbon footprint, according to IBM.

Meanwhile, the team plans to optimize the cooling structures for smaller chip dimensions, more interconnects and sophisticated heat transfer structures. In particular, the lab is experimenting with ways of adding extra cooling to the designated hotspots on cores.

Eventually, IBM envisions a hierarchy of cooling structures similar to those in the brain, which branch out to cover a large surface area combined with many interconnections among layers.